The present invention relates to ASIC design methodologies, and more particularly to a method for discovering power errors in ASIC designs during the design phase.
An application specific integrated circuit (ASIC) is a chip that is custom designed for a specific application, rather than a general-purpose chip such as a microprocessor. An ASIC chip performs an electronic operation as fast as it is possible to do so, providing, of course, that the circuit design is efficiently architected. One area of concern during fabrication is whether the power distribution system is designed correctly.
FIG. 1 is a block diagram illustrating a basic design flow for fabricating an ASIC. The design flow includes a front-end design process that creates a logical design for the ASIC, and a backend design process that creates a physical design for the ASIC. The front-end design process begins with providing a design entry 10 for an electronic circuit that is used to generate a high-level electronic circuit description, which is typically written in a Hardware Description Language (HDL) 12.
Interconnect data from previous designs are used to generate interconnect statistical data to use as the estimation of the physical properties for the interconnects in step 14. The interconnect statistical data is used to create a wire load model 16, which defines the resistance, capacitance, and the area of all nets in the design. The statistically generated wire load model 16 is used to estimate the wire lengths in the design and define how net delays are computed.
The HDL 12 and the wire load model 16 are then input into a logic synthesis tool 18 to generate a list of logic gates and their interconnections, called a layout database or xe2x80x9cnetlistxe2x80x9d 20. Next, system partitioning is performed in step 22 in which the physical design is partitioned to define groupings of cells small enough to be timed accurately with wire load models 16 (local nets). The resulting design typically includes many cells with many interconnect paths, with many having large fanins and fanouts. A prelayout simulation is then performed in step 24 with successive refinement to the design entry 10 and to logic synthesis 18 to determine if the design functions properly.
After prelayout simulation 24 is satisfactory, the backend design process begins with floorplanning in step 26 in which the blocks of the netlist 20 are arranged on the chip. The location of the cells in the blocks are then determined during a placement process in step 28. A routing process makes connections between cells and blocks in step 30. Thereafter, circuit extraction determines the resistance and capacitance of the interconnects in step 32. A postlayout simulation is then performed in step 34 with successive refinement to floorplanning 26 as necessary.
Although the physical knowledge of previous designs are incorporated early in the design flow, many design errors can occur, including the design of the power distribution structures. There are commercially available power tools for carrying out power analysis, but these tools are capable of only transistor and gate level analysis and are designed for use in the late stages of the design after the power structures are completed. Performing such low-level structural analysis late in the design phase can result in many post-layout design iterations to obtain correct power distribution in the finished logical and physical design. These additional design loops can add weeks or months to a project schedule and significantly increase the cost of the design.
Accordingly, what is needed is a tool for performing high-level structural analysis on ASIC designs to ensure that power design rules are adhered to so that power related problems can be avoided during the design flow. The present invention addresses such a need.
The present invention provides a method for checking power errors in an ASIC design. The method includes providing a power checker software program that has one or more power checker modules, where each module checks a particular type of power element in the ASIC design. A power checker database is also created that stores the following: individual power elements in the ASIC design, a connectivity graph of the power elements, and location bins corresponding to physical areas in ASIC design that identify the power elements that are located within each area. The method further includes providing a user with a choice of which power elements in the design to check, and executing the power checker modules corresponding to the selected power elements in order to check for errors in the selected power elements. Any detected errors are output for the user.
According to the system and method disclosed herein, the present invention provides a software tool can be used at any stage of power planning to check that the power rules are followed for the power elements. This enables power errors to be detected earlier in the design flow. Consequently, the number post-layout iterations required will be minimized, thereby reducing the cost of the design.